Many modern computing devices make use of input/output (I/O) adapters and buses that utilize some version or implementation of the Peripheral Component Interconnect (PCI) or PCI Express (PCIe) interconnect standards. The PCIe standard specifies a computer communication interconnect for attaching peripheral devices to a host computer. PCIe is an extension of the earlier PCI standard that uses existing PCI programming concepts, but bases the computer interconnect on a faster physical-layer communications protocol. The PCIe physical layer consists of dual uni-directional links between upstream and downstream devices.
Recently many devices connected using the PCIe standard now have a non-PCIe link in the communication path, which creates compatibility problems. For example, a PCIe compatible peripheral, such as a printer, may communicate with a host computer using PCIe over an intervening 802.11 wireless local area network. The PCIe standard addresses this possibility by defining PCIe switches (more generally referred to as tunnels) that are capable of isolating non-PCIe segments. Each of these tunnels has a PCIe port and a non-PCIe port, such that each tunnel can convert a PCIe packet into a non-PCIe packet or vice versa. Typically, two tunnels are utilized on a communication link that has a non-PCIe link. For packets originated by the host, the upstream tunnel converts PCIe packets to non-PCIe packets and the downstream tunnel receives the non-PCIe packets and converts them back to PCIe packets. For packets originated by the device, the tunnels reverse the flow. Unfortunately, during system configuration the root complex treats each tunnel port as a separate downstream device and assigns a unique identifier to each port.
The PCIe standard defines the identifiers as a combination of so-called “bus numbers” (to identify the point-to-point link segment since PCIe uses point-to-point links rather than buses), device Numbers, and function numbers. Because the PCIe standard requires downstream devices to have consecutively numbered bus numbers, the root complex typically assigns a range of bus numbers to the link to accommodate additional downstream PCIe devices which may be added after configuration. However, in today's world, many PCIe standard devices are connected to the root complex via downstream hubs such as wireless routers after configuration. Adding too many downstream devices can exhaust the pool of reserved bus numbers available for assignment, causing the system either to ignore the downstream devices added after all bus numbers are assigned, or to halt all operations and re-run the configuration process to reassign bus numbers before continuing operations.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items.